Microprocessor Interview Questions - 1

1. What is a Microprocessor?
Answer


2. Why does microprocessor contain ROM chips?
Answer

3. What is the difference between a microprocessor and a microcontroller?
Answer

4. Give examples for 8, 16, and 32 bit microprocessors.
Answer

5. Give an example of a microprocessor, whose structure is pipelined.
Answer

6. What is flag? Give some examples of a flag.
Answer

7. What are most common registers present in a microprocessor?
Answer

8. Why is address bus unidirectional?
Answer

9. Why is data bus bidirectional?
Answer

10. Expand RAM, ROM, PROM, EPROM, EEPROM.
Answer

Verilog Interview Questions - 1

Questions are related to comparison (What is the difference betweem ...).

1. What is the difference between a function and a task?
Answer


2. What is the difference between $display and $monitor?
Answer

3. What is the difference between wire and reg?
Answer

4. What is the difference between blocking and non-blocking assignments?
Answer

5. What is the difference between casex, casez and case statements?
Answer

6. What is the difference between transport delay and inertial delay?
Answer

7. What is the difference between unary and logical operators?
Answer

8. What is the difference between compiled, interpreted, event based and cycle based simulators?
Answer

9. What is the difference between ( = = , ! = ) and ( = = = , ! = = )?
Answer

10. What are the difference between Verilog and VHDL?
Answer

Basics: Lexical Tokens

>> Operators
>> Comments
>> Whitespace
>> Strings
>> Identifiers
>> Keywords
>> Number Specification


Operators


There are three types of operators: unary, binary, and ternary, which have one, two, and three operands respectively.

Unary : Single operand, which precede the operand.
Ex: x = ~y
~ is a unary operator
y is the operand

binary : Comes between two operands.
Ex: x = y || z
|| is a binary operator
y and z are the operands

ternary : Ternary operators have two separate operators that separate three operands.
Ex: p = x ? y : z
? : is a ternary operator
x, y, and z are the operands

List of operators is given here.

Comments

Verilog HDL also have two types of commenting, similar to that of C programming language. // is used for single line commenting and '/*' and '*/' are used for commenting multiple lines which start with /* and end with */.
EX: // single line comment
/* Multiple line
commenting */
/* This is a // LEGAL comment */
/* This is an /* ILLEGAL */ comment */

Whitespace

  • - \b - backspace
  • - \t - tab space
  • - \n - new line
In verilog Whitespace is ignored except when it separates tokens. Whitespace is not ignored in strings. Whitesapces are generally used in writing test benches.

Strings

A string in verilog is same as that of C programming language. It is a sequence of characters enclosed in double quotes. String are treated as sequence of one byte ASCII values, hence they can be of one line only, they cannot be of multiple lines.
Ex: " This is a string "
" This is not treated as
string in verilog HDL "

Identifiers

Identifiers are user-defined words for variables, function names, module names, block names and instance names.Identifiers begin with a letter or underscore and can include any number of letters, digits and underscores. It is not legal to start identifiers with number or the dollar($) symbol in Verilog HDL. Identifiers in Verilog are case-sensitive.

Keywords

Keywords are special words reserved to define the language constructs. In verilog all keywords are in lowercase only. A list of all keywords in Verilog is given below:

always
and
assign
attribute
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endattribute
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
ifnone
initial
inout
input
integer
join
medium
module
large
macromodule
nand
negedge
nmos
nor
not
notif0
notif1
or
output
parameter
pmos
posedge
primitive
pull0
pull1
pulldown
pullup
rcmos
real
realtime
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
signed
small
specify
specparam
strength
strong0
strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
trireg
unsigned
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor


Verilog keywords also includes compiler directives, system tasks, and functions. Most of the keywords will be explained in the later sections.

Number Specification

Sized Number Specification

Representation: [size]'[base][number]
  • [size] is written only in decimal and specifies the number of bits.
  • [base] could be 'd' or 'D' for decimal, 'h' or 'H' for hexadecimal, 'b' or 'B' for binary, and 'o' or 'O' for octal.
  • [number] The number is specified as consecutive digits. Uppercase letters are legal for number specification (in case of hexadecimal numbers).
Ex: 4'b1111 : 4-bit binary number
16'h1A2F : 16-bit hexadecimal number
32'd1 : 32-bit decimal number
8'o3 : 8-bit octal number

Unsized Number Specification

By default numbers that are specified without a [base] specification are decimal numbers. Numbers that are written without a [size] specification have a default number of bits that is simulator and/or machine specific (generally 32).

Ex: 123 : This is a decimal number
'hc3 : This is a hexadecimal number
Number of bits depends on simulator/machine, generally 32.

x or z values

x - Unknown value.
z - High impedance value
An x or z sets four bits for a number in the hexadecimal base, three bits for a number in the octal base, and one bit for a number in the binary base.

Note: If the most significant bit of a number is 0, x, or z, the number is automatically extended to fill the most significant bits, respectively, with 0, x, or z. This makes it easy to assign x or z to whole vector. If the most significant digit is 1, then it is also zero extended.

Negative Numbers

Representation: -[size]'[base][number]

Ex: -8'd9 : 8-bit negative number stored as 2's complement of 8
-8'sd3 : Used for performing signed integer math
4'd-2 : Illegal

Underscore(_) and question(?) mark

An underscore, "_" is allowed to use anywhere in a number except in the beginning. It is used only to improve readability of numbers and are ignored by Verilog. A question mark "?" is the alternative for z w.r.t. numbers
Ex: 8'b1100_1101 : Underscore improves readability
4'b1??1 : same as 4'b1zz1


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Basics: Number Specification

Sized Number Specification

Representation: [size]'[base][number]

  • [size] is written only in decimal and specifies the number of bits.
  • [base] could be 'd' or 'D' for decimal, 'h' or 'H' for hexadecimal, 'b' or 'B' for binary, and 'o' or 'O' for octal.
  • [number] The number is specified as consecutive digits. Uppercase letters are legal for number specification (in case of hexadecimal numbers).
Ex: 4'b1111 : 4-bit binary number
16'h1A2F : 16-bit hexadecimal number
32'd1 : 32-bit decimal number
8'o3 : 8-bit octal number

Unsized Number Specification

By default numbers that are specified without a [base] specification are decimal numbers. Numbers that are written without a [size] specification have a default number of bits that is simulator and/or machine specific (generally 32).

Ex: 123 : This is a decimal number
'hc3 : This is a hexadecimal number
Number of bits depends on simulator/machine, generally 32.

x or z values

x - Unknown value.
z - High impedance value
An x or z sets four bits for a number in the hexadecimal base, three bits for a number in the octal base, and one bit for a number in the binary base.

Note: If the most significant bit of a number is 0, x, or z, the number is automatically extended to fill the most significant bits, respectively, with 0, x, or z. This makes it easy to assign x or z to whole vector. If the most significant digit is 1, then it is also zero extended.

Negative Numbers

Representation: -[size]'[base][number]

Ex: -8'd9 : 8-bit negative number stored as 2's complement of 8
-8'sd3 : Used for performing signed integer math
4'd-2 : Illegal

Underscore(_) and question(?) mark

An underscore, "_" is allowed to use anywhere in a number except in the beginning. It is used only to improve readability of numbers and are ignored by Verilog. A question mark "?" is the alternative for z w.r.t. numbers
Ex: 8'b1100_1101 : Underscore improves readability
4'b1??1 : same as 4'b1zz1

The VLSI Design Flow

The VLSI IC circuits design flow is shown in the figure below. The various level of design are numbered and the gray coloured blocks show processes in the design flow.
Specifications comes first, they describe abstractly the functionality, interface, and the architecture of the digital IC circuit to be designed.

  • Behavioral description is then created to analyze the design in terms of functionality, performance, compliance to given standards, and other specifications.
  • RTL description is done using HDLs. This RTL description is simulated to test functionality. From here onwards we need the help of EDA tools.
  • RTL description is then converted to a gate-level netlist using logic synthesis tools. A gate-level netlist is a description of the circuit in terms of gates and connections between them, which are made in such a way that they meet the timing, power and area specifications.
  • Finally a physical layout is made, which will be verified and then sent to fabrication.

Introduction to Verilog HDL

>> Introduction
>> The VLSI Design Flow
>> Importance of HDLs
>> Verilog HDL
>> Why Verilog ?
>> Digital Design Methods


Introduction


With the advent of VLSI technology and increased usage of digital circuits, designers has to design single chips with millions of transistors. It became almost impossible to verify these circuits of high complexity on breadboard. Hence Computer-aided techniques became critical for verification and design of VLSI digital circuits.As designs got larger and more complex, logic simulation assumed an important role in the design process. Designers could iron
out functional bugs in the architecture before the chip was designed further. All these factors which led to the evolution of Computer-Aided Digital Design, intern led to the emergence of Hardware Description Languages.

Verilog HDL and VHDL are the popular HDLs.Today, Verilog HDL is an accepted IEEE standard. In 1995, the original standard IEEE 1364-1995 was approved. IEEE 1364-2001 is the latest Verilog HDL standard that made significant improvements to the original standard.


The VLSI Design Flow

The VLSI IC circuits design flow is shown in the figure below. The various level of design are numbered and the gray coloured blocks show processes in the design flow.
Specifications comes first, they describe abstractly the functionality, interface, and the architecture of the digital IC circuit to be designed.

  • Behavioral description is then created to analyze the design in terms of functionality, performance, compliance to given standards, and other specifications.
  • RTL description is done using HDLs. This RTL description is simulated to test functionality. From here onwards we need the help of EDA tools.
  • RTL description is then converted to a gate-level net list using logic synthesis tools. A gate-level netlist is a description of the circuit in terms of gates and connections between them, which are made in such a way that they meet the timing, power and area specifications.
  • Finally a physical layout is made, which will be verified and then sent to fabrication.

Importance of HDLs
  • RTL descriptions, independent of specific fabrication technology can be made an verified.
  • functional verification of the design can be done early in the design cycle.
  • Better representation of design due to simplicity of HDLs when compared to gate-level schematics.
  • Modification and optimization of the design became easy with HDLs.
  • Cuts down design cycle time significantly because the chance of a functional bug at a later stage in the design-flow is minimal.

Verilog HDL


Verilog HDL is one of the most used HDLs. It can be used to describe designs at four levels of abstraction:
  1. Algorithmic level.
  2. Register transfer level (RTL).
  3. Gate level.
  4. Switch level (the switches are MOS transistors inside gates).

Why Verilog ?
  • Easy to learn and easy to use, due to its similarity in syntax to that of the C programming language.
  • Different levels of abstraction can be mixed in the same design.
  • Availability of Verilog HDL libraries for post-logic synthesis simulation.
  • Most of the synthesis tools support Verilog HDL.
  • The Programming Language Interface (PLI) is a powerful feature that allows the user to write custom C code to interact with the internal data structures of Verilog. Designers can customize a Verilog HDL simulator to their needs with the PLI.

Digital design methods

Digital design methods are of two types:
  1. Top-down design method : In this design method we first define the top-level block and then we build necessary sub-blocks, which are required to build the top-level block. Then the sub-blocks are divided further into smaller-blocks, and so on. The bottom level blocks are called as leaf cells. By saying bottom level it means that the leaf cell cannot be divided further.
  2. Bottom-up design method : In this design method we first find the bottom leaf cells, and then start building upper sub-blocks and building so on, we reach the top-level block of the design.
In general a combination of both types is used. These types of design methods helps the design architects, logics designers, and circuit designers. Design architects gives specifications to the logic designers, who follow one of the design methods or both. They identify the leaf cells. Circuit designers design those leaf cells, and they try to optimize leaf cells in terms of power, area, and speed. Hence all the design goes parallel and helps finishing the job faster.


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